1. Field of the Invention
The present invention relates to hardware emulation of integrated circuits. In particular, the present invention relates to an emulator architecture implemented using serialized interconnections between programmable logic devices.
2. Discussion of the Related Art
Hardware emulation of integrated circuits is a method extensively used in the design process of complex logic circuits. A hardware emulator provides a substrate for implementing a complex logic circuit. Typically, the emulator includes as building blocks of the substrate one or more interconnected circuit boards. In each circuit board, a number of interconnected programmable logic devices are provided for implementing selected portions of the complex logic circuit. Field programmable gate arrays (“FPGAs”) are the most common programmable logic devices (“PLDs”) found in a hardware emulator. The hardware emulator is controlled by software running on a host processor, such as an engineering workstation.
To achieve hardware emulation of the complex logic circuit, a designer provides a description of the logic circuit in a hardware description language. In a modern hardware emulator, the description of the logic circuit can be provided as a behavior level description, a register transfer level (RTL) description (e.g., a verilog or VHDL description), or a logic gate level netlist. If a behavior or RTL level description is used, a logic gate level description for the circuit is synthesized. From the logic gate level description, the logic circuit is partitioned. Each partition is assigned to a PLD for realization. Signals between partitions implemented on different PLDs are transmitted over the pins of the PLDs. The physical signal paths for routing such signals depend on the how the PLDs are laid out and interconnected on each circuit board, and how the circuit boards are interconnected. In some emulators, partial cross bar switches are provided to route signals between PLDs. In other emulators, each PLD is directly connected to a fixed number of other PLDs directly, and another number of PLDs indirectly, according to a predetermined interconnection configuration. Often, signals between partitions implemented on different PLDs are routed through one or more intermediate PLDs.
In a large logic circuit implemented over multiple PLDs, the pins of the PLDs become a scarce resource that must be carefully allocated to avoid excessive signal delays and to maintain high resource utilization in the PLDs. Complex algorithms for placement of partitions and signal routing are devised to achieve these goals. However, a structural organization of the PLDs and their associated interconnection circuits that simplifies circuit placement and signal routing is desired.